Fin type transistors have been investigated for future generation of devices, such as tier sub-22 nm technology. This may be due to, for example, the fact that fin type transistors are conducive to high integration density. However, conventional fin type transistors exhibit high parasitic junction capacitance, which undesirably decrease performance. Additionally, conventional processes for forming fin type transistors result in large variations in height. This undesirably results in variations in device characteristics across the wafer, reducing reliability and yields.
From the foregoing discussion, it is desirable to provide a fin type device with improved performance and reduced variability.